The present specification relates to the fabrication of integrated circuits (ICs). More specifically, the present specification relates to a silylation patterning process for forming integrated circuit features.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultra violet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the coating through a photomask or reticle causes the image area to become selectively crosslinked and consequently either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble (i.e., uncrosslinked) or deprotected areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. As feature sizes are driven smaller and smaller, optical systems are approaching their limits caused by the wavelengths of the optical radiation.
One alternative to conventional projection lithography is EUV lithography. EUV lithography reduces feature size of circuit elements by lithographically imaging them with radiation of a shorter wavelength. xe2x80x9cLongxe2x80x9d or xe2x80x9csoftxe2x80x9d x-rays (a.k.a, extreme ultraviolet (EUV)), wavelengths in the range of 50 to 700 Angstroms are used in an effort to achieve smaller desired feature sizes.
In EUV lithography, EUV radiation can be projected onto a resonant-reflective reticle. The resonant-reflective reticle reflects a substantial portion of the EUV radiation which carries an IC pattern formed on the reticle to an all resonant-reflective imaging system (e.g., series of high precision mirrors). A demagnified image of the reticle pattern is projected onto a resist coated wafer. The entire reticle pattern is exposed onto the wafer by synchronously scanning the mask and the wafer (i.e., a step-and-scan exposure).
The photoresist material or layer associated with conventional lithographic technologies is often utilized to selectively form various IC structures, regions, and layers. Generally, the patterned photoresist material can be utilized to define doping regions, deposition regions, etching regions, or other structures associated with an integrated circuit (IC). A conventional lithographic system is generally utilized to project the pattern to the photoresist material or layer. The photoresist material may be either a positive or a negative photoresist layer.
In the case of a positive photoresist material or layer, the light causes photochemical reaction in the photoresist layer. The photoresist layer is removable with a developer solution at the portions of the photoresist that are exposed to light through a mask. The photoresist layer is developed to clear away those portions. An integrated circuit feature, such as a gate, via, or interconnect, is then etched or doped into the layer of material, and the remaining photoresist is removed. In the case of a negative photoresist material, the light causes the photoresist layer to be removable with a developer solution at portions of the photoresist layer that are not exposed to light through the mask.
Various types of photoresist materials are manufactured by a number of manufacturers. The photoresist material can include multiple photoresist films (i.e. a multi-level resist (MLR)). According to some conventional processes, the photoresist layer is provided over an anti-reflective coating (ARC), such as silicon nitride (Si3N4) or silicon oxynitride (SiON). The anti-reflective coating is disposed above the material which is to be processed.
Conventional processes have utilized a variety of resolution enhancement technologies for lithographically creating patterns which define lines and spaces. These processes include the use of phase shift masks, the use of reflow operations and the use of ultrathin photoresist layers. Conventional resolution enhancement technologies have not been utilized to provide contact holes or conductive vias. Attenuated phase shift masks are the only tool typically utilized to enhance the resolution associated with contact patterns. Therefore, contact patterns have been relatively large patterns.
According to conventional reflow processes, the photoresist layer is applied as a thick photoresist layer. Thick photoresist layers can have thicknesses over 0.5 microns. The thick photoresist layer is patterned. After patterning, the photoresist layer is developed and heated to a high temperature (e.g. between 120-170 degrees Celsius).
When heated, the photoresist layer becomes almost plasticized (e.g., viscous). The photoresist layer flows due to the higher temperatures associated with the heating step. The heating of the thick photoresist layer reduces the width associated with features in the resist pattern (the edges of the resist pattern flow closer together, thereby making a smaller hole or trench). After the photoresist layer has been heated (i.e., reflowed), conventional semiconductor processes are performed.
Reflow technologies require thick photoresist layers to ensure that a sufficient amount of material is available to reflow. The use of thick photoresist layers has an adverse effect on lithographic resolution. Variations in thickness uniformity can affect the precision associated with focusing the radiation on the photoresist layer (i.e., it is difficult to have a precise depth of focus when the photoresist layer is thick).
Other conventional processes have utilized ultrathin photoresist layers. Ultrathin photoresist layers have achieved greater resolution than thick photoresist layers. However, reflow technologies have not been applied to ultrathin photoresist layers because the ultrathin photoresist layer does not provide adequate material for the flow operation (the ultrathin photoresist layer is too thin to provide sufficient material to flow without compromising other areas of the photoresist layer).
Conventional integrated circuit fabrication techniques may also include a process known as silylation. For example, U.S. Pat. No. 6,107,177 describes a silylation method for protecting photoresist and preventing photoresist loss. Generally, silylation involves the introduction of a gas or a liquid containing silicon agents which react with silicon containing materials. Silicon containing agents include hexamethyl disilazane (HMDS), hexamethyl cyclotrisilazane, trimethylsilyl ethyl isocyanate and/or dimethysilyl dimethylamine. Silicon containing agents may be supplied as a gas in a dry silylation method. Alternatively, silylation may be provided by employing a wet chemistry method. Often, dry chemistries can provide a more uniform and controlled silylation process. Heretofore, a silylation process has not been utilized to significantly reduce critical trench dimensions.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need to form smaller feature sizes, such as, smaller contact holes. Yet further, there is a need for a hybrid photoresist reflow process and a silylation process. Even further still, there is a need for a hybrid silylation and ultrathin photoresist process. Yet even further, there is a need for a hybrid ultrathin photoresist layer and reflow process.
An exemplary embodiment relates to a method of fabricating an integrated circuit. The method includes providing a photoresist layer over a semiconductor substrate, forming an aperture in the photoresist layer, and silylating the photoresist layer. The aperture has a width which is decreased after silylating the photoresist layer. The method also includes reflowing the photoresist layer to further decrease the width of the aperture.
An exemplary embodiment also relates to a method of fabricating a contact for an integrated circuit. The method includes providing a photoresist layer over an insulating layer above a substrate, patterning the photoresist layer to remove a portion, silylating the photoresist layer, and reflowing the photoresist layer.
Still another embodiment relates to a method of forming narrow trenches in a layer of photoresist. The method includes providing a photoresist layer, patterning the photoresist layer to form apertures having sidewalls. The method also includes silylating sidewalls of the apertures in the photoresist layer and reflowing the photoresist layer.